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Results: 1614

#	Item
121	Transformer: A Functional-Driven Cycle-Accurate Multicore Simulator Zhenman Fang1,2 , Qinghao Min2 , Keyong Zhou2 , Yi Lu2 , Yibin Hu2 , Weihua Zhang2 , Haibo Chen3 , Jian Li4 , Binyu Zang2 1 The State Key Lab of ASIC & Add to Reading List Source URL: ipads.se.sjtu.edu.cn Language: English - Date: 2012-08-23 22:17:16 Parallel computing Central processing unit Computer architecture Instruction set architectures Microprocessors CPU cache Computer architecture simulator ARM architecture Multi-core processor Speedup Emulator Microcode
122	Applying Amdahl’s Other Law to the data center D. Cohen Add to Reading List Source URL: www.mulix.org Language: English - Date: 2016-05-15 08:07:24 Computer architecture Computer memory Hypervisor I/O virtualization Cache Virtualization Storage area network CPU cache Hyper-V Memory hierarchy Logical partition Direct memory access
123	Appears in the proceedings of the 34th International Symposium on Microarchitecture (MICRO), Dec. 3-Dec. 5, 2001, Austin, Texas. Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution Ravi Rajwar a Add to Reading List Source URL: pages.cs.wisc.edu Language: English - Date: 2001-10-10 12:33:46 Concurrency control Computing Computer architecture Test-and-set Transactional memory Non-blocking algorithm Synchronization Monitor Lock Linearizability Consistency model CPU cache
124	S CIEntIfIC ProgrAmmIng Editors: Konstantin Läufer, Add to Reading List Source URL: www.blosc.org Language: English - Date: 2014-07-07 14:11:47 Computing Computer memory Computer architecture Computer engineering Computer hardware Cache Parallel computing Central processing unit CPU cache Memory hierarchy Multi-core processor Locality of reference
125	Micro-Policies: Formally Verified Tagging Schemes for Safety and Security (Extended Abstract) C˘at˘alin Hrit¸cu (INRIA Paris)1 Today’s computer systems are distressingly insecure. A host of vulnerabilities arise fro Add to Reading List Source URL: software.imdea.org Language: English - Date: 2014-07-17 09:25:53 Computing Central processing unit Computer architecture Computer engineering Cache Instruction set Opcode Program counter Computer Tag CPU cache
126	On the Localness of Software Zhaopeng Tu Zhendong Su Prem Devanbu Add to Reading List Source URL: macbeth.cs.ucdavis.edu Language: English - Date: 2014-07-25 14:06:06 Computational linguistics Natural language processing Language modeling Speech recognition Linguistics Applied linguistics N-gram Cache language model Language model Cache Gram CPU cache
127	Opportunities for Parallelism in Matrix Multiplication FLAME Working Note #71 Tyler M. Smith∗ Robert A. van de Geijn∗ Add to Reading List Source URL: www.cs.utexas.edu Language: English - Date: 2014-01-10 19:11:37 Parallel computing Compiler optimizations Computer architecture CPU cache Central processing unit Computer memory Xeon Automatic parallelization Basic Linear Algebra Subprograms Nehalem Thread
128	Anatomy of High-Performance Many-Threaded Matrix Multiplication Tyler M. Smith∗ , Robert van de Geijn∗ , Mikhail Smelyanskiy† , Jeff R. Hammond‡ and Field G. Van Zee∗ ∗ Institute for Computational Engineerin Add to Reading List Source URL: www.cs.utexas.edu Language: English - Date: 2014-02-10 15:58:29 Computer architecture Parallel computing Compiler optimizations Cache Computer memory CPU cache Xeon Phi Multi-core processor Xeon Loop nest optimization Nehalem PowerPC A2
129	BugCache for Inspections : Hit or Miss? Foyzur Rahman Daryl Posnett Abram Hindle Add to Reading List Source URL: macbeth.cs.ucdavis.edu Language: English - Date: 2011-07-05 12:24:54 Cache Computing Software optimization Computer programming Computer memory Computer architecture Software bug Locality of reference Software testing Lookup table Debugging CPU cache
130	Ehcache v1.2.3 User Guide Greg Luck 2 September 2006 2 Add to Reading List Source URL: www.ehcache.org Language: English - Date: 2016-02-25 06:01:44 Cache Java enterprise platform Ehcache Object-relational mapping Distributed cache CPU cache Hibernate

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